1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.
2. Description of the Related Art
Conventionally, the mainstream of semiconductor device configuration has been that a single semiconductor device is equipped with a single semiconductor layer. In recent years, however, there have been proposed such semiconductor device configuration in which a single semiconductor device is equipped with a plurality of semiconductor layers. More specifically, it is possible to enhance the capabilities of a semiconductor device, including the processing speed, while reducing the size and weight of the semiconductor device as a whole by mounting a plurality of semiconductor layers in a multilayered manner within the single semiconductor device.
When manufacturing this multilayer-structured semiconductor device, it is necessary to laminate and electrically connect the semiconductor layers to one another within the semiconductor device. Hence, this plurality of semiconductor layers are electrically connected to one another through a contact plug.
FIGS. 15 to 17 illustrate a method for forming a common multilayer structure. First, as shown in FIG. 15A, semiconductor element 2 is formed on one surface of semiconductor substrate 1. In FIG. 15, an example is shown in which a planar-type MOSFET is formed as semiconductor element 2. Next, as shown in FIG. 15B, first interlayer insulating film 3 is formed on the side of semiconductor substrate 1 on which semiconductor element 2 is formed.
After this, as shown in FIG. 16A, there is formed mask pattern 4 including openings on first interlayer insulating film 3 in the positions thereof corresponding to the source/drain regions of the planar-type MOSFET. Next, using this mask pattern 4 as a mask, contact holes 5 are formed so as to penetrate through first interlayer insulating film 3 up to the source/drain regions. Next, as shown in FIG. 16B, mask pattern 4 is removed and then a conductive material is buried in the contact holes, thereby forming contact plugs 6.
After this, as shown in FIG. 17A, second interlayer insulating film 7 is further formed on first interlayer insulating film 3. Then, there is formed mask pattern 8 including an opening on second interlayer insulating film 7 in the position thereof corresponding to either one of the source/drain regions of the planar-type MOSFET. Next, contact hole 9 is formed so as to penetrate through second interlayer insulating film 7. Next, as shown in FIG. 17B, a conductive material is buried in contact hole 9, thereby forming contact plug 10.
In recent years, there has been a progress in the miniaturization of such a multilayer structure as described above and, therefore, it has become increasingly difficult to align a contact plug with a desired region to establish contact when forming the contact plug. Hence, a study has been made of a method capable of aligning a contact plug with high accuracy.
In the method described in Japanese Patent Laid-Open No. 5-114658, a contact hole for connecting a plurality of conductive layers is formed, and then a film consisting primarily of silicon is buried in the contact hole. After this, the film consisting primarily of silicon is left over so as to cover a contact hole opening, and then a metal film for forming a second conductive layer is formed. The document states that by forming this metal film, it is possible to use the step difference of the film consisting primarily of silicon as an index for alignment in a photolithography step of forming an interconnect and, thereby, increase the alignment accuracy of the interconnect in the second conductive layer.
In the method described in Japanese Patent Laid-Open No. 10-27845, a silicon dioxide film and a silicon nitride film are formed on a semiconductor substrate including a lower interconnect layer, and then the silicon nitride film in a region in which an interconnect layer is to be formed is selectively etched away, thereby forming a trench. After this, photoresist A is formed in this trench and photoresist B including a hole in a region in which a contact hole is to be formed is further formed. Subsequently, photoresist A in this position is removed to expose the silicon dioxide film. Then, using this photoresist B and the silicon nitride film as masks, the silicon dioxide film in the region in which the contact hole is to be formed is selectively removed to expose the lower interconnect layer, thereby forming a contact hole. Japanese Patent Laid-Open No. 10-27845 states that in the method described therein, high-precision alignment is possible by forming the masks composed of photoresist B and the silicon nitride film in such a stepwise fashion as described above.
Along with the progress of equipment miniaturization, high integration, and diversification of equipment design in recent years, it has been necessary, in some cases, to include a step of aligning a contact hole from the rear surface side of a semiconductor substrate. I have now discovered that a related method for forming a contact plug, however, had limitations in the accuracy of aligning the contact hole due to, for example, an alignment error arising when forming a mask pattern by photolithography. The recent progress in the miniaturization of a semiconductor device, in particular, has given rise to a demand for high accuracy also in the alignment of a contact plug with a semiconductor element. Failure to carry out such alignment with high accuracy has, in some cases, led to a short-circuit between the contact plug and the semiconductor substrate and between the contact plug and the gate electrode thereof. Furthermore, the methods described in Japanese Patent Laid-Open Nos. 5-114658 and 10-27845 have had limitations in alignment accuracy.